Results concerning an R&D study for a specialized processor capable of precisely reconstructing,
in pixel detectors, hundreds of charged-particle tracks from high-energy collisions at 40 MHz rate are presented.
A highly parallel pattern-recognition algorithm, inspired by studies of the processing of visual images by the brain,
and described in detail an efficient hardware implementation in FPGA devices is applied.
We find that offline-grade tracking in large detectors is possible with sub-microsecond latencies.
This is the first detailed demonstration of reconstruction of tracks at 40 MHz and makes the device
suitable for processing Large Hadron Collider events at the full crossing frequency.